ScicosHDL v.6

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Scicos-HDL integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. Scicos-HDL shortens digital circuit design cycles by helping you create the hardware representation in an modeling-friendly development environment. You can combine existing Scicos blocks with Scicos-HDL blocks and to link system-level design . It is a open source project under Scilab ???‚?s license, the release vision can help to design and simulate some small-scale digital circuit system with its Hardware Description Language generation. We now will make it as a tool for teaching digital circuit design. Now it supports SystemC, VHDL&Verilog Languages.Features: Links The Scilab/Scicos with the Digital circuit design(EDA). Integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. Enables complex signal processing combined with powerful mathematical tools. Inside libraries: Sequential logic library, Combinational logic library, Ipcore library, simulation library. Support mixed-simulation with the Scicos blocks. Automatically generates Description Language(SystemC ,VHDL and Verilog ). Automatic propagation of signal names to generated HDL. You can specify most values in the block parameter dialog boxes using Scicos workspace. Mix-simulation with original Scicos blocks and Scicos-HDL blocks. Open interface for users to add blocks. Under GPL LICENCE.

Scicos-HDL integrates the hardware circuit, ...

 
  • ScicosHDL
  • 6
  • scicoshdl
  • Linux
  • Freeware
  • 20.16 Mb
  • 268
  • Free
 
 

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